0, NONE, , invalid opcode
1, LOAD.pri, address, PRI = [address]
2, LOAD.alt, address, ALT = [address]
3, LOAD.S.pri, offset, PRI = [FRM + offset]
4, LOAD.S.alt, offset, ALT = [FRM + offset]
5, LREF.pri, address, PRI = [ [address] ]
6, LREF.alt, address, ALT = [ [address] ]
7, LREF.S.pri, offset, PRI = [ [FRM + offset] ]
8, LREF.S.alt, offset, ALT = [ [FRM + offset] ]
9, LOAD.I, , PRI = [PRI] (full cell)
10, LODB.I, number, PRI = "number" bytes from [PRI] (read 1/2/4 bytes)
11, CONST.pri, value, PRI = value
12, CONST.alt, value, ALT = value
13, ADDR.pri, offset, PRI = FRM + offset
14, ADDR.alt, offset, ALT = FRM + offset
15, STOR.pri, address, [address] = PRI
16, STOR.alt, address, [address] = ALT
17, STOR.S.pri, offset, [FRM + offset] = PRI
18, STOR.S.alt, offset, [FRM + offset] = ALT
19, SREF.pri, address, [ [address] ] = PRI
20, SREF.alt, address, [ [address] ] = ALT
21, SREF.S.pri, offset, [ [FRM + offset] ] = PRI
22, SREF.S.alt, offset, [ [FRM + offset] ] = ALT
23, STOR.I, , [ALT] = PRI (full cell)
24, STRB.I, number, "number" bytes at [ALT] = PRI (write 1/2/4 bytes)
25, LIDX, , PRI = [ ALT + (PRI * cell size) ]
26, LIDX.B, shift, PRI = [ ALT + (PRI << shift) ]
27, IDXADDR, , PRI = ALT + (PRI * cell size) (calculate indexed address)
28, IDXADDR.B, shift, PRI = ALT + (PRI << shift) (calculate indexed address)
29, ALIGN.pri, number, Little Endian: PRI ^ = cell size
30, ALIGN.alt, number, Little Endian: ALT ^ = cell size
31, LCTRL, index, PRI is set to the current value of any of the special registers. The index parameter must be: 0=COD, 1=DAT, 2=HEA,3=STP, 4=STK, 5=FRM, 6=CIP (of the next instruction)
32, SCTRL, index, set the indexed special registers to the value in PRI. The index parameter must be: 2=HEA, 4=STK, 5=FRM, 6=CIP
33, MOVE.pri, , PRI = ALT
34, MOVE.alt, , ALT = PRI
35, XCHG, , Exchange PRI and ALT
36, PUSH.pri, , [STK] = PRI, STK = STK 
37, PUSH.alt, , [STK] = ALT, STK = STK 
38, PUSH.R, value, Repeat value: [STK] = PRI, STK = STK 
39, PUSH.C, value, [STK] = value, STK = STK 
40, PUSH, address, [STK] = [address], STK = STK 
41, PUSH.S, offset, [STK] = [FRM + offset], STK = STK 
42, POP.pri, , STK = STK + cell size, PRI = [STK]
43, POP.alt, , STK = STK + cell size, ALT = [STK]
44, STACK, value, ALT = STK, STK = STK + value
45, HEAP, value, ALT = HEA, HEA = HEA + value
46, PROC, , [STK] = FRM, STK = STK 
47, RET, , STK = STK + cell size, FRM = [STK], STK = STK + cell size, CIP = [STK], The RET instruction cleans up the stack frame and returns from the function to the instruction after the call.
48, RETN, , STK = STK + cell size, FRM = [STK], STK = STK + cell size, CIP = [STK], STK = STK + [STK] The RETN instruction removes a specifed number of bytes from the stack. The value to adjust STK with must be pushed prior to the call.
49, CALL, address, [STK] = CIP + 5, STK = STK The CALL instruction jumps to an address after storing the address of the next sequential instruction on the stack.
50, CALL.pri, , [STK] = CIP + 1, STK = STK 
51, JUMP, address, CIP = address (jump to the address)
52, JREL, offset, CIP = CIP + offset (jump offset bytes from currentposition)
53, JZER, address, if PRI == 0 then CIP = [CIP + 1]
54, JNZ, address, if PRI != 0 then CIP = [CIP + 1]
55, JEQ, address, if PRI == ALT then CIP = [CIP + 1]
56, JNEQ, address, if PRI != ALT then CIP = [CIP + 1]
57, JLESS, address, if PRI < ALT then CIP = [CIP + 1] (unsigned)
58, JLEQ, address, if PRI < = ALT then CIP = [CIP + 1] (unsigned)
59, JGRTR, address, if PRI > ALT then CIP = [CIP + 1] (unsigned)
60, JGEQ, address, if PRI > = ALT then CIP = [CIP + 1] (unsigned)
61, JSLESS, address, if PRI < ALT then CIP = [CIP + 1] (signed)
62, JSLEQ, address, if PRI < = ALT then CIP = [CIP + 1] (signed)
63, JSGRTR, address, if PRI > ALT then CIP = [CIP + 1] (signed)
64, JSGEQ, address, if PRI > = ALT then CIP = [CIP + 1] (signed)
65, SHL, , PRI = PRI << ALT
66, SHR, , PRI = PRI >> ALT (without sign extension)
67, SSHR, , PRI = PRI >> ALT with sign extension
68, SHL.C.pri, value, PRI = PRI << value
69, SHL.C.alt, value, ALT = ALT << value
70, SHR.C.pri, value, PRI = PRI >> value (without sign extension)
71, SHR.C.alt, value, ALT = ALT >> value (without sign extension)
72, SMUL, , PRI = PRI * ALT (signed multiply)
73, SDIV, , PRI = PRI / ALT (signed divide), ALT = PRI mod ALT
74, SDIV.alt, , PRI = ALT / PRI (signed divide), ALT = ALT mod PRI
75, UMUL, , PRI = PRI * ALT (unsigned multiply)
76, UDIV, , PRI = PRI / ALT (unsigned divide), ALT = PRI mod ALT
77, UDIV.alt, , PRI = ALT / PRI (unsigned divide), ALT = ALT mod PRI
78, ADD, , PRI = PRI + ALT
79, SUB, , PRI = PRI - ALT
80, SUB.alt, , PRI = ALT - PRI
81, AND, , PRI = PRI & ALT
82, OR, , PRI = PRI | ALT
83, XOR, , PRI = PRI ^ ALT
84, NOT, , PRI = !PRI
85, NEG, , PRI = PRI = --PRI
86, INVERT, , PRI = ~ PRI
87, ADD.C, value, PRI = PRI + value
88, SMUL.C, value, PRI = PRI * value
89, ZERO.pri, , PRI = 0
90, ZERO.alt, , ALT = 0
91, ZERO, address, [address] = 0
92, ZERO.S, offset, [FRM + offset] = 0
93, SIGN.pri, , sign extent the byte in PRI to a cell
94, SIGN.alt, , sign extent the byte in ALT to a cell
95, EQ, , PRI = PRI == ALT ? 1 : 0
96, NEQ, , PRI = PRI != ALT ? 1 : 0
97, LESS, , PRI = PRI < ALT ? 1 : 0 (unsigned)
98, LEQ, , PRI = PRI < = ALT ? 1 : 0 (unsigned)
99, GRTR, , PRI = PRI > ALT ? 1 : 0 (unsigned)
100, GEQ, , PRI = PRI > = ALT ? 1 : 0 (unsigned)
101, SLESS, , PRI = PRI < ALT ? 1 : 0 (signed)
102, SLEQ, , PRI = PRI < = ALT ? 1 : 0 (signed)
103, SGRTR, , PRI = PRI > ALT ? 1 : 0 (signed)
104, SGEQ, , PRI = PRI > = ALT ? 1 : 0 (signed)
105, EQ.C.pri, value, PRI = PRI == value ? 1 : 0
106, EQ.C.alt, value, PRI = ALT == value ? 1 : 0
107, INC.pri, , PRI = PRI + 1
108, INC.alt, , ALT = ALT + 1
109, INC, address, [address] = [address] + 1
110, INC.S, offset, [FRM + offset] = [FRM + offset] + 1
111, INC.I, , [PRI] = [PRI] + 1
112, DEC.pri, , PRI = PRI - 1
113, DEC.alt, , ALT = ALT - 1
114, DEC, address, [address] = [address] - 1
115, DEC.S, offset, [FRM + offset] = [FRM + offset] - 1
116, DEC.I, , [PRI] = [PRI] - 1
117, MOVS, number, Copy memory from [PRI] to [ALT]. The parameter specifes the number of bytes. The blocks should not overlap.
118, CMPS, number, Compare memory blocks at [PRI] and [ALT]. The parameter specifes the number of bytes. The blocks should not overlap.
119, FILL, number, Fill memory at [ALT] with value in [PRI]. The parameter specifes the number of bytes, which must be a multiple of the cell size.
120, HALT, 0, Abort execution (exit value in PRI), parameters other than 0 have a special meaning.
121, BOUNDS, value, Abort execution if PRI > value or if PRI < 0
122, SYSREQ.pri, , call system service, service number in PRI
123, SYSREQ.C, value, call system service
124, FILE, size ord name..., source file information pair: name and ordinal (see below)
125, LINE, line ord, source line number and file ordinal (see below)
126, SYMBOL, sze off flg name..., symbol information (see below)
127, SRANGE, lvl size, symbol range and dimensions (see below)
128, JUMP.pri, , CIP = PRI (indirect jump)
129, SWITCH, address, Compare PRI to the values in the case table (whose address is passed) and jump to the associated address.
130, CASETBL, ... , casetbl num default num*[case jump]
131, SWAP.pri, , [STK] = PRI and PRI = [STK]
132, SWAP.alt, , [STK] = ALT and ALT = [STK]
133, PUSHADDR, offset, [STK] = FRM + offset, STK = STK 
134, NOP, , no-operation, for code alignment
135, SYSREQ.N, address n, macro: PUSH.C n ; SYSREQ.C adr ; STACK n+4
136, SYMTAG, value, symbol tag
137, BREAK, , invokes optional debugger
138, PUSH2.C, c1 c2, macro: replaces two PUSH.C opcodes
139, PUSH2, a1 a2, macro: replaces two PUSH opcodes
140, PUSH2.S, o1 o2, macro: replaces two PUSH.S opcodes
141, PUSH2.ADR, o1 o2, macro: replaces two PUSH.ADR opcodes
142, PUSH3.C, c1 c2 c3, macro: replaces three PUSH.C opcodes
143, PUSH3, a1 a2 a3, macro: replaces three PUSH opcodes
144, PUSH3.S, o1 o2 o3, macro: replaces three PUSH.S opcodes
145, PUSH3.ADR, o1 o2 o3, macro: replaces three PUSH.ADR opcodes
146, PUSH4.C, c1 c2 c3 c4, macro: replaces four PUSH.C opcodes
147, PUSH4, a1 a2 a3 a4, macro: replaces four PUSH opcodes
148, PUSH4.S, o1 o2 o3 o4, macro: replaces four PUSH.S opcodes
149, PUSH4.ADR, o1 o2 o3 o4, macro: replaces four PUSH.ADR opcodes
150, PUSH5.C, c1 c2 c3 c4 c5, macro: replaces five PUSH.C opcodes
151, PUSH5, a1 a2 a3 a4 a5, macro: replaces five PUSH opcodes
152, PUSH5.S, o1 o2 o3 o4 o5, macro: replaces five PUSH.S opcodes
153, PUSH5.ADR, o1 o2 o3 o4 o5, macro: replaces five PUSH.ADR opcodes
154, LOAD_BOTH, a1 a2, PRI = [a1] ; ALT = [a2]
155, LOAD_S_BOTH, o1 o2, PRI = [FRM + o1], ALT = [FRM + o2]
156, CONST, adr val, [adr] = val
157, CONST_S, off val, [FRM + off] = val
158, SYSREQ_D, ,The pawn compiler never generates it. They are generated by the abstract machine itself
159, SYSREQ_ND, ,The pawn compiler never generates it. They are generated by the abstract machine itself
160, SM_TRACKER.PUSH.C, [value], [TRACKER] = value, TRACKER++
161, SM_TRACKER.POP.SETHEAP, , TRACKER--, HEA -= [TRACKER]
162, SM_GENARRAY, [n], generate an n dimensional array; more details http://www.sourcemod.net/devlog/?p=106
163, SM_GENARRAY.Z, [n], generate an n dimensional array; more details http://www.sourcemod.net/devlog/?p=106
